Internal: Schnorr's Lower Bound for XOR Circuits #
This internal module proves Schnorr's lower bound via the CircDesc model.
The public definitions (Schnorr.xorBool, Schnorr.xorBool_flip,
Schnorr.xorBool_essential) are in Circ.XOR. The public theorem
schnorr_lower_bound_circuit is accessible through Circ.Schnorr.
CircDesc Insensitivity #
theorem
CircuitComplexity.Schnorr.wireValD_eq_of_unreferenced
{N s : ℕ}
(d : CircDesc N s)
(a : Fin N)
(b : Bool)
(hno : ∀ (g : Fin s), ↑(d g).2.1.1 ≠ ↑a ∧ ↑(d g).2.1.2 ≠ ↑a)
(x : BitString N)
(w : Fin (N + s))
(hw : ↑w ≠ ↑a)
:
If no gate references input a, wire values are unchanged when a is modified.
Circuit Restriction #
Gate Elimination #
How to redirect references to an eliminated gate.
- const {W : ℕ} (c : Bool) : GateRedirect W
- wire {W : ℕ} (w : Fin W) (flip : Bool) : GateRedirect W
Instances For
def
CircuitComplexity.Schnorr.elimGateD
{N s : ℕ}
(d : CircDesc N (s + 1))
(g : Fin (s + 1))
(rd : GateRedirect (N + s))
:
CircDesc N s
Remove gate g from a CircDesc, redirecting references to it.
Equations
- One or more equations did not get rendered due to their size.
Instances For
theorem
CircuitComplexity.Schnorr.evalD_elimGateD
{N s : ℕ}
(d : CircDesc N (s + 1))
(hs : 0 < s)
(g : Fin (s + 1))
(rd : GateRedirect (N + s))
(hrd :
∀ (x : BitString N),
wireValD d x ⟨N + ↑g, ⋯⟩ = match rd with
| GateRedirect.const c => c
| GateRedirect.wire w flip => flip ^^ wireValD d x ⟨↑w, ⋯⟩)
(hrd_wire : ∀ (w' : Fin (N + s)) (flip : Bool), rd = GateRedirect.wire w' flip → ↑w' < N + ↑g)
(hg_not_last : ↑g < s)
(x : BitString N)
:
Restriction eliminates two gates #
XOR needs ≥ 3 gates #
theorem
CircuitComplexity.Schnorr.restriction_eliminates_two
{n s : ℕ}
(d : CircDesc (n + 1) s)
(hs : 0 < s)
(hn : 0 < n)
(comp : Bool)
(heval : ∀ (x : BitString (n + 1)), evalD hs d x = (comp ^^ xorBool (n + 1) x))
(hessential : ∀ (a : Fin (n + 1)) (x : BitString (n + 1)), evalD hs d x ≠ evalD hs d (Function.update x a !x a))
:
Key inductive step: restricting one variable of a totally essential XOR circuit yields a circuit for XOR on one fewer input, with at least 2 fewer gates.