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LeanPool.BooleanMultiplication.N4.SevenGate

Algebraic exclusion of seven gates #

A seven-gate circuit computing Mul 4 would have no defect: its final wire space contains the sixteen-dimensional space Aff + T, while seven gates can raise the affine dimension by at most seven. Thus every intermediate wire lands in Aff + T. The rational-prefix closure theorem then traps every gate in Aff + R, contradicting the presence of a non-rational target direction.

This argument uses neither circuit enumeration nor a truth-table search.

Seven gates leave no room for a direction outside Aff + T.

The purely algebraic seven-gate lower bound used by normalization.

The defect budget of eight gates is attained. If it were zero, the same rational-prefix trap used above would contain the entire target space.

Attaining target rank seven and defect one forces every one of the eight gate outputs to be a genuinely new wire-space direction.